The invention relates to a semiconductor component and a production method suitable therefor.
In the semiconductor technology, what are known as “chip-on-chip” components have been known for a long time and are used for an extremely wide variety of purposes. These semiconductor components are distinguished by the fact that they have at least two chips or semiconductor elements layered above one another that are connected electrically to one another by means of corresponding contact-making regions. Layering the chips/semiconductor elements above one another permits the production of extremely compact semiconductor components.
In the following text, with reference to FIG. 1, a “chip-on-chip” semiconductor component of this type will be described. A semiconductor component 1′ has a housing 2, from which first and second electrical leads 3a and 3b, which are used as external terminals, are led out. Provided in the housing 2 is a mounting device 4, which is used simultaneously as a heat sink and as a contact region for a drain terminal and also as a carrier for the entire arrangement mounted thereon. Fitted to the mounting device 4 is a first chip 5 which, for example, contains a plurality of transistors. Fitted to the first chip 5 are a second chip 6 and a third chip 7, which are each connected electrically to the first chip 5 by means of a contact-making region (here: a first contact-making layer 8 and a second contact-making layer 9). The surfaces of the second and third chips 6, 7 in each case form source contacts, the source contact of the second chip 6 being connected to the first electrical lead 3a via a first bonding wire 10. In a manner corresponding to this, the source contact of the third chip 7 is connected to the second lead 3b via a second bonding wire 11. The first contact-making layer 8 is connected to the first lead 3a by means of a third bonding wire 12, and in a manner corresponding to this, the second contact-making layer 9 is connected to the second lead 3b by means of a fourth bonding wire 13. The first contact-making layer 8 forms a source contact for the first chip 5 and, at the same time, the drain contact for the second chip 6. In a corresponding way, the second contact-making layer 9 forms a source contact for the first chip 5 and the drain contact for the third chip 7.
The semiconductor component illustrated in FIG. 1 has the disadvantage that a first contact-making area 14 on the first contact-making layer 8 for forming a contact between the third bonding wire 12 and the first contact-making layer 8 is relatively large, so that an extent of the second chip 6 horizontally in the direction of the first lead 3a is limited. Analogous considerations apply to a second contact-making area 15 on the second contact-making layer 9.